Keifer is the codename for a planned server microprocessor by Intel that will have 32 cores arranged in 8 nodes. Each node will have 3 mebibytes of shared L3 cache and 512 kibibytes of shared L2 cache. Each node will contain a memory controller to reduce latency and increase bandwidth to main memory. This represents a departure from Intel's current strategy of placing the memory controller on the northbridge. Intel hopes that Keifer will surpass the performance of Sun Microsystems' UltraSPARC series of multi-core processors in 2010.

Keifer is planned to be built using the 32 nanometer process.